1. Field of the Invention
The present invention relates to a microcomputer having a processor and a memory formed on the same chip, and more particularly, it relates to the layout of a processor and a memory as well as a transfer unit for performing data transfer between these processor and memory.
2. Description of the Background Art
FIG. 1 is a diagram schematically showing an exemplary structure of a conventional processing system. Referring to FIG. 1, the processing system includes a processor 1 performing required arithmetic and logic processing operations, and a main memory 1 provided in the exterior of the processor 1 and serving as a main storage for this processor 1. The processor 1 is connected to the main memory 2 through an external data bus 3. This main memory 2 stores instructions and processed or pre-processed data (hereinafter both are referred to as information).
The processor 1 includes a cache memory 1a for storing information, a controller 1b forming various control signals in accordance with the information stored in this cache memory 1a, a register group 1c for temporarily storing data required for arithmetic and logic processing, and an arithmetic unit 1d performing required operations in accordance with the control signals from the controller 1d. The cache memory 1a, the controller 1b, the register group 1c and the arithmetic unit 1d are interconnected with each other through an internal data bus 1e. This internal data bus 1e is connected to the external data bus 3 through an interface 1f. The interface 1f manages data transfer between the main memory 2, the cache memory 1a and the controller 1b under control of this controller 1b.
When the controller 1b requires information which is not stored in the cache memory 1a in the structure of this processing system shown in FIG. 1, the information required by this controller 1b is transferred from the main memory 2 through the external data bus 3 and the interface 1f.
The main memory 2, which is formed by a DRAM (dynamic random access memory) of a large storage capacity, for example, cannot operate at such a high speed as the processor 1. The speed of data transfer between the main memory 2 and the processor 1 is determined by the bus width (bit width) of the external data bus 3. The bus width of the external data bus 3 is determined by the number of data input/output terminals of the main memory 2. Thus, there arises such a problem that the data transfer between the main memory 2 and the processor 1 cannot be performed at a high speed, the processor I is entered into a wait state in the data transfer with this main memory 2, and the performance of the processing system reduces.
In order to solve the problem resulting from the low-speediness of the main memory 2 in this processing system shown in FIG. 1, it is conceivable to form the processor 1 and the main memory 2 on the same chip for widening the bus width of the external data bus 3 to perform the data transfer at a high speed.
FIG. 2 is a diagram schematically showing an exemplary structure of such a microcomputer that a processor and a main memory are formed on the same chip. Referring to FIG. 2, the microcomputer 10 includes a cache memory 1a, a controller 1b, a register group 1c and an arithmetic unit 1d, similarly to the structure shown in FIG. 1. This microcomputer 10 further has a built-in main memory 2. The cache memory 1a, the controller 1b, the register group 1c, the arithmetic unit 1d and the main memory 2 are interconnected with each other through an internal data bus 11. This internal data bus 11 is connected to an external data bus through an interface unit 12 to perform transfer of information with an external unit.
By providing the main memory 2 in the microcomputer 10, information with the bus width (bit width) of this internal data bus 11 can be transferred without being subjected to restriction of the number of data input/output terminals of the main memory 2, dissimilarly to the structure shown in FIG. 1. Therefore, a large quantity of information can be simultaneously transferred and high-speed data transfer can be implemented by widening the bus width of this internal data bus 11. Further, the load capacitance of the internal data bus 11 is sufficiently small as compared with the load capacitance of the external data bus 3 which is an on-board wire shown in FIG. 1, and information transfer can be performed between the main memory 2, the cache memory 1a and the controller 1b at a higher speed. At this time, an output circuit of the main memory 2 is not required to drive a large load capacitance since the load capacitance of the internal data bus 11 is small, and current consumption of the processing system is reduced.
When performing transfer of information with the external unit in the structure of this microcomputer shown in FIG. 2, however, the interface unit 12 occupies the internal data bus 11. Thus, there arises such a problem that the controller 1b cannot utilize this internal data bus 11 during access to the main memory 2 by the interface unit 12, for example, arithmetic or logic operations stop during this period and the processing performance of the microcomputer reduces.
In such a microcomputer having a built-in memory, further, there is a sufficient room for further consideration as to what internal bus arrangement makes it possible to efficiently perform information transfer in the interior at a high speed.
There is also sufficient room for further consideration as to how to arrange the processor, the main memory and the interface unit to implement efficient information transfer in the interior of the microcomputer at a high speed and improving the processing performance.